System for the transmission of analog signals by means of pulse code modulation using non-recursive filters

ABSTRACT

A pulse code modulation system utilizes one digital filter before the digital compressor in the transmitter and a digital device which includes digital filters after the digital expander in the receiver, thereby eliminating the necessity for input and output analog filters in the transmitter and receiver, respectively.

United States Patent Bellanger et a1.

SYSTEM FOR THE TRANSMISSION OF ANALOG SIGNALS BY MEANS OF PULSE CODEMODULATION USING NON-RECURSIVE FILTERS Inventors: Maurice GeorgesBellanger, Antony;

Jacques Lucien Daguet, St. Maur both of France Assignee:Telecommunications Radioelectriques et Telephoniques T.R.T., Paris.France Filed: Nov. 9, 1973 Appl. No: 414,375

Related US. Application Data 179/15 AV, 1555 R Sept. 9, I975 [56]References Cited UNITED STATES PATENTS 2.9115116 111/1959 Hughes 179/15AV 3.3613477 H1968 Krcer Jr. 179/1555 R 3,560,659 2/1971 Grccikcs 325/42Primary Examiner-George H. Libmzlrl Attorney, Agent, or Firm-Frank R.Trifari; Simon L. Cohen 10 Claims. 12 Drawing Figures 1 2 3 4 S t f I 3"j 7 B Q (U l 12 N 1 Q, M

l CODER DIG1TAL DIGITAL DIITAL (DIGITAL c005 DECODER F lLTER COMPRESSOREXPANDER DEVICE CONVERTER PATENTH] SEP 9 975 SHEET 1 OF 7 DECODER R E TWm M 0V 7 AII O M C E m 6/ l Lt 3 Lm D 5) M lmm X E I! II R M w L S I m33mm R m HF z m R E 1 m Fig.1

INVENTKIR. MAURICE G. BELLANGER JACQUES DAGUET hTfiNTtlfi 9W5 3.904.963

sum 2 or 7 INVENTOR. MAURICE G. BELLANGER Y JACQUES L- DAGUETPATENTEDSEP 9|975 3,904,968

MEI [If I 10 CODE GROUP j 14 DISTRIBUTOR MULTIPLIER MULTIPLIER 15 13MEMORY Bin x 11 16 FILTER 18 17 jFlLTER do 40R w 0R N J N At At \-DELAYDELAY Fig.6

INVENTOR.

MAURICE G- BELLANGER BY JACQUES L- DAGUET AGENT PATENTEH 9% 90 2 SEES?swung Il]lllJL ]l MAURICE G- BELLANGER JACQUES L. DAGUET AGENT SYSTEMFOR THE TRANSMISSION OF ANALOG SIGNALS BY MEANS OF PULSE CODE MODULATIONUSING NON-RECURSIVE FILTERS This is a continuation of application Ser.No. 262,14l filed June 12, 1972, now abandoned, which was a continuationof application Ser. No. 61,342, filed Aug. 5, 1970, and now abandoned.

The invention relates to a system for the transmission of analog signalsby means of pulse code modulation in which the analog signal at thetransmitter end is converted into code groups characterizing the analogsignal with the aid of a coder, which code groups are transmitted aftercompression in a digital compressor, and in which the transmitted codegroups at the receiver end are converted into the original analog signalwith the aid of a decoder after expansion in a digital expander.

In such systems, which are particularly suitable for use in timedivision multiplex transmission systems, it is common practice that theanalog signal is applied to the coder through an input filter and thatthe analog signal at the output of the decoder is derived through anoutput filter. The requirements which these filters must satisfy arevery stringent. These filters must have a very sharply defined cut-off,a slight attenuation within the passband and a very large attenuationoutside the passband in order to avoid at the transmitter end thatfrequencies located outside the passband can return to the band, and tosuppress occurring image frequencies at the receiver end. A seriousdrawback is that the above-mentioned stringent requirements for thefilters can only be satisfied by filters which are built up from aplurality of sections provided with coils and which therefore requiregreat care and accurate adjustment during manufacture, which makes thesefilters comparatively expensive. In practice these filters have theadditional drawback that they are sensitive to temperature influencesand ageing phenomena.

An object of the present invention is to provide a novel conception of asystem of the kind described in the preamble in which the input andoutput filters provided with coils are entirely avoided, which novelconception makes it additionally possible to give the entire system anintegrated form so that a considerable economy in cost and a greaterreliability can be obtained. According to the invention the coder at thetransmitter end is formed in such a manner that the code groupscharacterizing the analog input signal occur at a frequency which is atleast four times the maximum frequency of the analog signal and whichcode groups consist of a certain number of bits which occur in series atthe output of the coder, while a digital filter is incorporated betweensaid coder and said compressor, which filter is formed as a low pass andhalf band filter of the non-recursive type so that the frequency of thecode groups at the output means is half the frequency of the code groupsat the input means while at the receiver end in such a system at leastone digital device is incorporated between the digital expandor and thedecoder, which digital device increases the frequency of the code groupsapplied to the filter by means of interpolation up to an outputfrequency which is at least an even multiple of the input frequency ofthe code groups.

In a preferred embodiment of the system according to the invention thedigital filter used at the receiver end is formed in such a manner thatthe code groups appearing at the output of the device occur at afrequency which is at least four times the input frequency of the codegroups, while in addition a device built up from logic elements isincorporated between the filter and the decoder, which device convertsthe pulse code modulation into delta pulse code modulation bysubtracting successive code groups from each other.

In order that the invention may be readily carried into effect someembodiments thereof will now be described in detail by way of examplewith reference to the accompanying diagrammatic drawings in which FIG. 1shows the principle diagram of the system according to the invention,

FIG. 2 shows a time diagram to explain the operation of the coder usedin the system according to FIG. 1,

FIG. 3 shows the two scales and their mutual relationship used in thecoder,

FIGS. 40, 4b and 4c show the transfer characteristic of a digital filterused in the system according to FIG. 1, a number of code groups appliedto the input of the filter and the inverse Fourier transformations ofthe filter transfer characteristic,

FIG. 5 shows the principle circuit diagram of the digital filter used atthe transmitter end,

FIG. 6 shows the principle circuit diagram of the digital filter used atthe receiver end,

FIG. 7 shows a portion of the decoder used in the system according toFIG. 1,

FIG. 8 shows a time diagram to explain the operation of the decodershown in FIG. 7,

FIG. 9 shows an embodiment of an integrator having double time constantsused in the decoder and FIG. 10 shows for the purpose of illustrationthe analog output signals supplied by the integrator according to FIG.9.

In the system for the transmission of analog signals by means of pulsecode modulation as shown in FIG. I the part to the left of the verticalbroken lines represents the transmitter. This transmitter includes acoder 2 to whose input terminal I the analog signal to be transmitted isapplied and which coder supplies code groups which characterize theanalog signal and which are transmitted after compression in a digitalcompressor 4 to the receiver which is shown in FIG. I to the right ofthe vertical broken lines. In this receiver the transmitted code groupsare applied after expansion in a digital expandor 5 to a decoder 8 withwhich the original analog signal is recovered. In accordance with theinvention a particularly favourable and altogether advantageousconception of such a system is obtained if the said coder 2 is formed insuch a manner that the code groups characterizing the analog inputsignal occur at a frequency which is at least four times the maximumfrequency of the analog input signal and which code groups comprise acertain number of bits which occur in series at the output of the coderand if between this coder 2 and this compressor 4 a digital filter 3 isincorporated which filter is formed as a low pass and half band filterof the non-recursive type so that the input maximum frequency is halfthe input maximum frequency, and if furthermore at least a digitaldevice 6 is incorporated at the receiver end between the digitalexpandor S and the decoder 8, which digital filter increases thefrequency of the code groups applied to the filter by means ofinterpolation up to an output frequency which is at least an evenmultiple of the input frequency of the code groups.

In the system shown in FIG. 1 the coder 2 is formed by a four-slopecoder in which the analog signal is applied to a duration modulatorwhich is provided with two integrating networks having mutually greatlydifferent time constants for pulse duration modulation in accordancewith four different slopes and in which the code groups are derived froma counter connected to the integrators. Such a four-slope coder isdescribed in greater detail in US. Ser. No. 7,635, filed Feb. 2, [970now U.Sv Pat. No. 3,674,931, issued July 4, 1972. In the coder describedin this Patent, the third slope commences after the end of the secondslope. The coder 2 used in the system according to FIG. 1 isdistinguished therefrom in that the third slope in each conversionperiod commences at a fixed constant so that the conversion period maybe better utilized. This conversion period is 125 micro seconds as isshown in the time diagram of FIG. 2a and starts whenever a control pulse1,. occurs. FIGS. 2b and 2(- show the variation of the out put voltagesof the first and second integrators while FIGS. 2d and 2e show thevariation of the output voltages as occur at the outputs of thecomparators which compare the integrator output voltages with areference level. This reference level is shown in FIG. 2d for the outputvoltage of the first integrator by means of a chain-link line.

In this case the two integrators are each connected to counters whichare active one after the other during half a period of the conversionperiod of 125 p. see. In this way it is achieved that the coder suppliesa code group over every half period of 62.5 usec. which code groupconsists of twelve bits in series. The frequency at which these codegroups occur at the output is then 16,000 per second, that is to say,four times the maximum frequency of the analog input signal. It isachieved in a very simple manner in the coder that the bits of the codegroups occur in series at the output with the least important bit first.After conversion of a sample of the analog output signal the twocounters of the coder together comprise the twelve bits which as a codegroup are representative for the amplitude of the analog signal at theinstant of sampling. In order to cause these bits to occur in series atthe output of the coder with the least important bit first, the twocounters are temporarily modified to form shift registers so that itbecomes possible to cause the bits to occur in series at a clockfrequency at the outputs of these registers. During the next conversionperiod the counters again have their original counting function. Thismodification of the counters to form registers is effected with the aidof a logic control signal which acts through a number of gates on themutual connections between the bistable elements of the counters. Whenthese devices are active as a counter the clock signal is only appliedto the first bistable element of the counter which has the smallestweight and the Q output of each bistable element is connected to theinput of the next bistable element to which the clock signal is applied.The inputs J and K of the bistable elements then have a fixed polarity.During the conversion period this device operates as a counter.Subsequently, at the end of the conversion period, the clock signal issuppressed and the counter has a certain counting content. The clocksignal is then applied to the clock pulse inputs of all bistableelements as a result of the control pulse and with the interposition ofthe previously mentioned gates and the outputs Q and 6 of each bistableelements are connccted to the inputs J and K, respectively, of the firstbistable element (smallest weight). It will be evident that the countersare modified into shift registers in this manner, The bits originallypresent in the counters will thus occur in series and the smallestweight first at the output Q of the first bistable element (smallerweight) during the period of duration of the control pulse.

The coder 2 used in this system is additionally distinguished by thedivision of the scales and the centring of the zero position. Thisfour-slope coder produces the analog-to-digital conversion by means oftwelve bits in two successive stages employing two scales which areshown in FIG. 3. The first scale has 64 steps of great weight for thefirst six bits; and the other scale has 128 steps of small weight. 64steps of the second scale precisely fit in one step of the large scalewhich is diagrammatically shown by the two oblique lines shown in FIG.3. Since the second scale has 128 steps, it may easily be variedrelative to the first scale when it is influenced, for example, bytemperature without this exerting influence on the signal-to-noise ratiobecause always only 64 small steps correspond to one big step.

FIG. 3 shows that the zero position corresponding to an analog signal 0and chosen for the coder, which position is shown by the broken-line ofintersection and the two scales, is located on the first scale betweenthe 31st and 32nd steps and between the 63rd and 64th steps on thesecond scale. The steps covered on this second scale range from 32 to96. In this zero position the coder supplies the code group 0] l l l l ll l l l l 2047 (centre of a scale of 4096 steps enumerated O to 4095).This means that the coder determines the sum of3l X 64+63 =2047.

On the other hand the steps of the second scale located about the zeroposition (in the vicinity of 63) are covered when a weak signal isapplied to the input of the coder. The first scale will always give thesame indication as long as the input signal applied to the coder has avalue measured from peak to peak which does not exceed 64 small steps.Since 64 small steps together have the value of one big step, that is tosay, they correspond to 1/64 part of the value which may be applied as amaximum to the input of the coder without saturation occurring, theratio 1/64 exactly defines the limit of the segment which includes theorigin in case of a normal digital compressor of l3 segments.Nonlinearity phenomena may occur at the transition of the two scales,that is to say, when one step upwards or downwards is effected on thefirst scale as a result of the fact that all possible steps in one orthe other direction on the second scale have been covered.

By using the steps 32 to 96 on the second scale and adjusting the zeroposition in the centre of the second scale (that is to say, the centreof the segment of the compression characteristic passing through theorigin) a coder may be obtained which is purely linear for weak signals.The non-linearity phenomena only occur when a segment is changed, whichis less unfavourable for the signal-to-noise ratio.

As explained in the foregoing 12 bits of code groups occur at the outputof the coder at a frequency which is at least four times the maximumfrequency of the analog input signal, that is to say, the code groupsoccur at a frequency of l6,000 per second when this maximum frequency is4 kHz. The clock frequency is 2048 kHz.

The 12 bits of code groups are transformed with the aid of a wry simpledevice (not shown) by means of zero additions into 16-bit code groups,the transformation consisting of. for example. the addition of at leasttwo zeros at the commencement and the end of the code word of twelvebits.

The digital filter which is denoted by the reference numeral 3 in FIG. Iis of the type without a feedback circuit and is therefore very stable.As described. the code groups applied to this filter comprise 16 hits inseries only l2 bits of which have any significance. The other four bitsserve as an addition so as to achieve a format of sixteen bits so thatit becomes possible to use dynamic memories in the filter. The use ofthis type of memory has the special advantage that four phase logics maybe used as is known. for example, from an article in "Mull-ard TechnicalCommunications". May I969. pages 2bb-27b and whose circuits areparticularly suitable for large-scale integration.

As is known a dynamic memory consists of a shift register the output ofwhich may be fed back to the input by a control signal so that when apiece of infor mation consisting of a series of n bits is completelywritten in in the register and when subsequently the output is fed backto the input by a control signal occurring at that instant, this pieceof information starts to circulate in the register under the control ofclock pulses until the said control signal is interrupted. Thus theregister operates as a memory. The contents of the register thenaccurately correspond periodically every time after 11 clock pulses or amultiple of n to the original information uhich is written in and whichcan consequently be read out periodically.

When using these registers in the filter the code groups to be writtenin in the register occur one after the other at a frequency of 16.000per second. that is to say. at a time interval which is equal to 128clock pulse intervals (clock pulse frequency 2048 kHz). For a correctuse of these registers it is required that the number of n bits of thesecode groups is a full submultiple of I28. This is the case when n lo andnot when n II.

FIG. 4a shows in the amplitude-frequency sector the filter transfercharacteristic of the low-pass filter to he obtained. The cut-offfrequency of this filter is at 4.000 H7. corresponding to the maximumfrequency of the analog signal to be transmitted.

FIG. 4/: shows in the amplitude-time sector the successive PCM signalswhich are applied to the filter and which occur at a frequency of 16,000per second. thus at a period t 62.5 usec. These PCM signals have thefollowing values:

5., at the instant I 8,. S S; S,, at the instants r T.

.S' Sc 54;, S.,, at the instants I l T.

ru =2T.re ,-"=3'l'.

FIG. 40 shows in the amplitude-time sector and at the same time scale asin FIG. 4b the inverse F urier transformation of the filter transfercharacteristic of the filter to be obtained. At the instantscorresponding to those of the PCM signals shown in FIG. 4h this inverseFourier transformation is defined by the coefficients:

A,, at the instant I 0 A,, A. A,-, A,, at the instants and L, L, and r1;, and re;

1,, and t n odd number.

It may be noted that at the instants 1,, "T and 1 n'l' the coefficientshave the value of zero when n even and differs from 0.

It is known per se (see, for example. the handbook System Analysis byDigital Computer" by F. F. Kuo and J. K. Kaiser. chapter 7) that anon-recursive filter having a transfer characteristic defined by theinverse Fourier transformation may be obtained by the follow ingelaboration of the code groups applied to the input of the filter:

in which A,, is representative for the coefficients of the inverseFourier transformation at the instants when the code groups 5,, and S.occur. The result (1' of this elaboration is the filtered code grouptaking into account the input code groups 8,, S;,. S- 5,. S.,. S. S... S,1

It may be noted with reference to FIG. 4(- that the coefficients A,, areequal to 0 for the even values of n with the exception of n 0 where A,,assumes the value A...

The elaboration to be performed thus is:

f T A S S *7 for I1 odd.

When a certain variation of the passband of the filter and a non-finitesharply defined cut-off is admitted. the number of coefficients A,, usedfor the calculation of b becomes finite.

When. for example. three coefficients A,, A A are taken the calculationto be performed for the filter will be equal to the finite sum:

FIG. 5 shows the filter 3 according to the invention in a block diagramand formed as the case taken as an Example in which three coefficientsA,. A A are used. The bits of the code groups consisting of lo bitsappear in series at the input of the filter 3. A known device It) refersthe code groups of odd serial number to the multipliers l1, l2. 13 whichmultiply these code groups simultaneously by the coefficients A,, A Arespectively. The code groups of even serial number are referred tomultiplier 14 which multiplies these code groups by the coefficient A,,.The result of the multiplication of the code groups of even serialnumber is stored in a memory 15 and will be used after the odd codegroups following this even code group have also been multiplied by A A AFurthermore. the filter includes six registers RI. R2, R3, R4, R5, R6and five combination devices ml, m2. m3. m4, m5. An input of thecombination device ml is connected to the output of the register RI andthe output of ml is connected to the input of R2. The combinationdevices m2. m3. m4. m5 are connected in the same way between rcspec'tively the register (R2. R3). (R3. R4). (R4. R5 I. {R23 R6). The outputofthe multiplier I3 is connected to the input of the register RI and toan input of the device m5. The output of the multiplier [Z is connectedto an input of the combination devices ml and 11:4. The out put ofmultiplier ll is connected to an input of the combination devices m2 andm3. Furthermore. the output of the memory 15 is connected to a thirdinput of the combination device m3. In this way. each time an odd codegroup occurs to the input of the filter, this code groups is multipliedby Al A3 A5 by means of multipliers ll, l2. l3 and after thesemultiplications the contents of the registers simultaneously changed asmentioned below:

the result of the multiplication by A is stored in R,

- the contents of R, are combined with the result of the multiplicationby A and are stored in R the contents of R are combined with the resultof the multiplication by A, and are stored in R,,.

the contents of R are combined with the result of the multiplication byA, and with the result of the multiplication by A which is present inthe memory 15; the result of this combination is stored in R thecontents of R are combined with the result of the multiplication by Aand are stored in R the contents of R are combined with the result ofthe multiplication by A and are stored in R,,.

the contents of R leave the filter so as to be further handled by thecompressor 4 of FIG 1.

The successive stages of operation which are performed in the filterwill be explained hereinafter while assuming for the sake of claritythat the following code groups occurring in the given sequence areconcerned: S;,, S, i .S,, S S which occur at the input of the filterwith the code group 5 first.

Furthe rmore it has been assumed that the registers R, to R,, and thememory [5 are empty at the instant when the code groups R;, comes in.The following elaboration proves that a digital number is obtained atthe instant 1;, in the register R,;. which number is equal to the value(b mentioned in the foregoing.

At the instant t the multiplication of 5,, by A, A

A is effected whereafter the result of these multiplications is directlywritten in in the registers R,. R R, R,. R R It is necessary to noteonly the digital value which is written in the register R because at theinstant t it will be the only value present in the output register R Thecontents of register R, are S A At the instant the multiplication of S,by A, is effected. The product S,A,, is written in in the memory andwill be used for the next elaboration. The contents of the registers areunchanged.

- At the instant I the multiplication of 8;, by A,, A A and combinationof the products 5 A,. 5 A, S,,A with the contents of the registers iseffected in the manner as described in the foregoing. It is necessary tonote only the contents of the register R after this instant Is becausethis is the only value which will be present at the instant ta in theregister R,,. These contents of R are 8 A S,,A,,.

At the instant r 5 A,, is written in in the memory 15.

At the instant 1,: the contents of R are present in the output registerR which contents are equal to: (S -,A a al i i- At the instant 0: S,,A,.is written in in the memory [5.

At the instant 1a,: the contents of register R correspond to thecontents of register R, which are equal to the sum of three values: thecontents of R 5 A,, S,,A;, S,A, the product S,,A,,, the product SA,A,.After the instant t the contents of R, thus are: S A, 3 1 ,1 l l- At theinstant t the contents of R are: S;,A 5 A,,

+ l l o o -l l 3 At the instant t the contents of R are: S A S,,A,, S,A,S,,A,, S ,A, S -,A,, S ,,A that is to say the desired value (1),. Thevalue (1),,- occurs at the output of the filter at a frequency which isequal to the rhytum by which the odd code groups occur at the input ofthe filter, hence at a frequency of 8,000 per second.

During the time intervals when the registers R, to R are not written inor read out these registers keep their contents by functioning as adynamic memory. The memory 15 is likewise constituted by a dynamicmemory. The multipliers of the filter are likewise constituted by suchregisters and by combination devices which may be formed in known mannerby an assembly of gates. Thus it can be stated that the filter consistsof registers and gates which, as is known, are suitable for large-scaleintegration. The digital filter which is used at the receiver endaccording to the invention is formed in a corresponding manner and istherefore likewise suitable for large-scale integration. This filterwhich is denoted by the reference numeral 6 in FIG. I receives codegroups of l6 bits each in series from the expandor 5 at a frequency of8,000 per second. that is to say. at a duration per code group of ,uscc.

FIG. 6 shows a block diagram of the digital device 6 used at thereceiver end. This device 6 comprises two units 16 and 17. The filter 16provides the filtered code groups at a frequency which corresponds tothe rhythm in which these code groups are applied to the input. that isto say, a frequency of 8,000 per second, which code groups appearing atthe output constitute a value which is interpolated in a point locatedat a mutually equal distance between the successive code groups ap pliedto the filter. The output of this filter F, is connected to an OR gate18 while the input of this filter is likewise connected through a delaycircuit 19 to this OR gate 18 with the aid of which the code groupsoccurring at the output of the delay circuit 19 are inserted between thecode groups occurring at the output of the filter 16 so that code groupsat a frequency of l6.000. that is to say. at a duration of 62.5 uscc percode group occur at the output of the OR gate 18.

The filter 17 connected to the OR gate operates in the same manner asthe filter 16 but with double the number of the code groups applied tothe input. This filter provides the code groups at a frequency of 16000.which code groups constitute an interpolated value in a point which islocated at a mutually equal distance from two successive code groupsapplied to the input Finally code groups which occur at a frequency of32.000 with a duration of 3 l .25 [1. sec per code group are obtained atthe output of OR gate 20 with the aid of OR gate 20 and delay circuit21. These code groups are formed by code groups applied to the input ofthe device 6 and code groups which are interpolated in three pointslocated at mutually equal distances hetween two successive code groupsapplied to the input of the device 6.

The filtering process of obtaining code groups which are interpolated ina point which is located at mutually equal distances from two successivecode groups applied to the input of the filter 16 will be describedhereinafter. This process largely corresponds to that of the filterwhich is used at the transmitter end. The transfer characteristic of thefilter is defined by its inverse Fourier transformation as isillustrated by the curve in FIG. 40 This curve is defined by thecoefficients A A A A The filter 16 is, however, distinguished from thefilter used at the transmitter end to which the code groups are appliedat a frequency of 16,000 per second and which code groups are on the onehand of an odd order such as. S S S S S S i v and on the other hand ofan even order such as i S S 8 5, S namely in that the filter 16 receivesthe code groups at a frequency of 8,000 per second, that is to say,exclusively code groups which are of an odd order such as 5-,. 3,. Se SS whose instants of occurrence are shown in PK]. 41). It follows thatthe function to be realized by the filter 16 which, according to thehandbook by Kuo and Kaiser mentioned in the foregoing. have the generalform:

The term A which occurred in the filter used at the transmitter end hasdisappeared in this case because 5,,

The device used for obtaining the filter l6 largely corresponds to thedevice used for the filter at the transmitter end and shown in FIG. 5.The device of the filter 16 is, however, different in that neither thedevice for separating the code groups of even and odd order is used. northe multiplier 14 and the memory 15 connected thereto.

As regards operation of the filter 16 the process starts every time atthe instants when code groups occur at the input, which process hasalready described hereinbcfore for the filter used at the transmitterend, that is to say, the multiplication of the code groups applied tothe input by the coefficients A,, A A and writing in the results ofthese multiplications in the registers added to the contents of eachprevious register. If only six successive code groups 5 S S S S 3, S..applied to the input of the filter are considered, the calculation willcommence at the instant 1;, and the desired result (b will be after theinstant in the register R This code group of the value 4),, isrepresentative for a code group interpolated at the instant t= 0 whichas regards time is located at an equal distance from the instants t andr 1, the interpolation being performed while taking into account thecode groups S 5;. S passed and the code groups 5. S-;;. 5d which arestill to come after the instant I It will be evident that the code groupd) cannot be obtained earlier than after the instant I when the codegroup Se is applied to the filter. The code groups (1),, occur at theoutput of the filter 16 at a frequency of 8,000 per second and have aduration of 62.5 u see each which corresponds to half the duration of acode group applied to the input of the filter.

in order to insert the code groups of the value (1),; occurring at theoutput of the filter 16 between the code groups applied to the input ofthe filter, the period should be taken into account which is necessaryfor performing the calculation of these code groups (b When inconformity with the embodiment qb is representative for the code groupinterpolated at the instant O, the value it) will not occur at theoutput of the filter until half a period after the instant L hence at adelay of three times the duration of a code group applied to the inputof the filter (375 1.1. sec). The delay circuit 19 serves to introducethis delay and makes it therefore possible to insert the code groupsoccuring at the input of the filter at the correct instants between thecode groups occuring at the output of the filter.

The filter 17 of FIG. 6 performs the same operations as the filter 16;this filter is formed in the same manner, the coefficients of theinverse Fourier transformation of this filter 17 are determined startingfrom the transfer characteristic of the entire filter (l6 and 17) usedat the receiver end. The filter 17 provides [6,000 code groups persecond which after the insertion of the code groups applied to the inputof the filter results in a succession of 32,000 code groups per second.

it will be evident that the device 6 used at the receiver end is readilysuitable for large-scale integration because this filter is built upfrom two filters l6 and 17 which are each formed in the same manner asthe filter used at the transmitter end.

The decoder 8 of FIG. 1 of the embodiment described of the systemaccording to the invention is a decoder of the type which reacts topulse density variations. This type of decoder has the advantage that itis suitable for large-scale integration except for the analog part whichis formed in this case by a single integrator operating with two timeconstants and providing the original analog signal. In addition thisdecoder has the advantage that it operates at the same standardised frequency as the coder, namely a clock frequency of 2048 kHz.

The code groups applied to the input of the decoder are provided in theembodiment shown by a device 7 of FIG. 1 which converts the pulse codemodulation into delta pulse code modulation by subtracting successivecode groups from each other. These are code groups which occur at afrequency of 32,000 per second and which are formed by twelve bits inseries one of which indicates the sign.

The six bits of small weight and the six bits of large weight of eachapplied code group are simultaneously converted into two independentdensity-modulated pulse trains in the digital part of the decoder.

FIG. 7 shows a block diagram of the device used for converting one ofthe two groups of six bits in a densitymodulated pulse train. Thisdevice includes six inhibi tor memories M M M M, M M each of which canstore a bit, six AND gates indicated by P P P v P an OR gate P andfinally a bistable clement D which provides the pulse train S and itscomplement g for controlling the integrator operating with two timeconstants.

The signals denoted by FF,, FF FF FF}, in FIG. 8 are applied to the saidAND gates P to P which signals are generated with the aid of a digitalcounter (not shown) comprising six bistable elements to the firstelement of which the clock-pulse of a fre quency of 2048 kHz andindicated by H in FIG. 8 are applied. The AND gates P to P.,- arecontrolled by these signals in such a manner that they perform thefollow- In FIG. 8 the signals occurring as a result of said logicelaboration at the output of the respective AND gates are denoted by P PP P These signals, which during the period d which comprises 64 clockpulse periods, that is 3 L75 p. see, are then given the weights 32168-4-2-l.

The signals P,, P P P, only occur at the output of the AND gates P, to Pwhen these do not receive an inhibitor signal from the inhibitormemories M M M i M connected to the respective inputs of the AND gates Pto P It will be readily evident from FIGS. 7 and 8 that when the sixbits which are written in in the inhibitor memories M, M M; M occur inthe rhythm of (1/6) which is the rhythm in which the code groups areapplied to the decoder and occur at the respective inputs of the ANDgates P to P a pulse train occurs at the output of the OR gate P whosetotal duration during the period 9 is representative for the value ofthe group to be decoded and consisting of six bits.

The pulses of this pulse train are symmetrically distributed over theperiod 6 relative to the centre of the period. The bistable element Dwhich is controlled at the clock frequency of 2048 kHz causes the phaseof the pulses occurring at the output of the OR gates P to be restoredand provides the signals S and which are applied to the integrator.

The device shown in FIG. 7 converts, for example. the six bits of smallweight into duration. The conversion of the group of six bits of largeweight is effected simultaneously with the aid of a device formed in thesame manner. In that case the same counter built up of six bistableelements is used for these two devices so that finally two independentdensity-modulated pulse trains S for the six bits of small weight and Sfor the six bits of large weight are obtained.

It has already been noted in the foregoing that the de vice 7 of FIG. Iwhich converts the pulse code modulation into delta pulse codemodulation by subtracting the successive code groups from each otherprovides code groups consisting of twelve bits one bit of whichindicates the sign. After the conversion into duration describedhereinbefore, these code groups are con verted into their absolutevalues by addition of the hinary number lOOOOOlOOOOO so that the zeroadjustment of the decoder (input signal 0) is in the centre of thelinear region likewise as in the coder.

The decoder is linear only when the device which converts the six bitsof small weight is active. For weak signals whose peak-to-peak amplitudeis not larger than the sum of the six bits of small weight theconversion into duration is thus linear.

As FIG 9 shows the signals S and S and their complements and are appliedto switches C, and C which as a function of these signals apply eitherthe voltage or the voltage n to the input of he inte grator employingtwo time constants FIG. 10 shows the diagrams of the signals which occurat the output of the integrator when a signal of zero amplitude isapplied to the input of the decoder. Diagram a shows the signal whichoccurs at the output of the OR gates associated with the bits of largeweight and those associated with the bits of small weight. Diagram bshows the signal which occurs at the output of the integrator as aresult of the bits oflarge weight. Dia gram 6 shows the output signalwhich occurs as a result of the bits of small weight (amplitude H/64 inwhich H F peak-to-peak amplitude). Diagram d shows the sum of thesesignals, and this signal has a constant mean value during an interval of3 L25 p. see; this mean value is brought to zero by adjustment of thevalue of the voltage +V in relation to V,,. The voltage +V follows thevoltage V,, by the interposition of an operational amplifier and aresistance bridge which makes it possible to adjust the values of +V insuch a manner that the output voltage of the integrator assumes a meanvalue of 0 volt in the absence of a signal at the input of the decoder.In this way the switching phenomena and the bias voltage of theoperational amplifier are compensated. The integrator is provided with acapacitor C which is shunted by a resistor r which automaticallystabilizes the mean 'value of the low frequency output signal of theintegrator.

The system according to the invention has the advantage that the commoninput and output filters can be omitted except for one RC network andthat the system as a whole is suitable for large-scale integration. Thedescribed embodiment has the additional advantage that the technologywhich is most advantageous in this respect may be used, that is to say.the technology employing so-called four-phase logics which is suitablefor field effect transistors and separate gates and in which only aminimum number of outputs is necessary because the bits of each codegroup are applied in series which is of special advantage because therealization of outputs as such is difficult and therefore has a costincreasing effect.

What is claimed is:

I. A system for the transmission of analog signals by means of a pulsecode modulation, comprising a transmitter and a receiver, saidtransmitter comprising means to sample said analog signal at four timesthe maximum information frequency to be transmitted of said analogsignal, a coder coupled to said sampling means to convert linearly saidsampled signals to code groups comprising serial bits, 3 digital filtercoupled to said coder, said digital filter being formed as a low pass.half band filter of the non-recursive type, and a digital compressorcoupled to said digital filter, said receiver comprising a digitalexpander having an output which is similar to the input to said digitalcompressor, a digital filtering device for interpolating between codegroups at the input means thereof to produce output code groups at atleast four times the frequency of the input code groups thereof. saiddigital filtering device comprising a plurality of non-recursivefilters, and a dc coder being coupled to said digital filtering devicefor generating an output signal which is a reproduction of said analogsignal.

2. A transmitter for the transmission of analog signals by means of apulse code modulation. comprising means to sample said analog signal atleast four times the maximum information frequency of said analogsignal. a coder coupled to said sampling means to convert linearly saidsampled signals to code groups comprising serial bits, a digital filtercoupled to said coder being formed as a low pass. half band filter ofthe nonrecursive type, and a digital compressor coupled to said digitalfilter.

3. A transmitter as claimed in claim 2, wherein said eoder comprises afour-slope coder in which said sampled signal is applied to a durationmodulator comprising two integrating networks having greatly differingtime constants for pulse duration in accordance with four differenceslopes, the three slopes of which commences at a fixed instant duringeach conversion period, means to derive l2-bit code groups coupled tosaid integrating networks, said duration modulator comprising twodigital counters coupled to said integrating networks respectively, saiddigital counters being active one after the other during a half aconversion period and are thereafter converted into a shift register inorder to supply the bits of a code group stored therein in parallel as aserial bit output signal.

4. A transmitter as claimed in claim 3, wherein the Zero point of saidconversion is located in the center of its linear region, said regioncorresponding to 64 times the bit of the smallest weight.

5. A transmitter as claimed in claim 2, wherein said digital filtercomprises means to separate code groups into code groups of even orderand code groups of odd order, a multiplier in which the code groups ofeven order are multiplied by a predetermined weight coefficient themagnitude of which is determined from the central transfer co efficientof said digital filter, a plurality of multipliers in which code groupsof odd order are multiplied by predetermined weight coefficients whosemagnitudes are determined from the odd transfer co-efficients of saiddigital filter, and a cascade circuit of dynamic memories andcombination devices for combining the output signals of said multipliersin a predetermined manner.

6. A receiver for a pulse code modulated signal comprising an analogsignal encoded as compressed digitally code groups, said receivercomprising a digital expander, a digital filter device for interpolatingbetween code groups at the input means thereof to produce output codegroups at least four times the frequency of the input code groupsthereof, said digital filtering device comprising non-recursive filtersand a decoder, said decoder being coupled to said digital device forgenerat ing an output signal which is a reproduction of said analogsignal.

7. A receiver as claimed in claim 6, further comprising means to convertthe pulse code modulation signal 1() from said digital filtering deviceinto delta pulse code modulation by subtracting successive code groupsfrom each other, said conversion means being between said digitalfiltering device and said decoder.

8. A receiver as claimed in claim 7, wherein said digi- 15 tal filteringdevice comprises a cascade circuit of two devices each of said devicescomprising a non-recursive digital filter, a delay circuit connected tothe input means of said digital filter and an OR-gate connected to theoutput means of said digital filter, the output means of said delaycircuit being connected to said OR- gate whereby code groups present atthe output means of said digital filter and code groups present at theoutput means of said delay circuit alternate with each other.

9. A receiver as claimed in claim 8, wherein said nonrecursive digitalfilter comprises a plurality of multipliers in which code groups at thefilter input are multiplied by predetermined weight co-efficients whosemagnitudes are determined from the odd transfer co- 3 efficients of saiddigital filter, and a cascade circuit of dynamic memories andcombination device for combining the output signal of said multipliersin a predetermined manner.

10. A receiver as claimed in claim 7, wherein said decoder comprises adevice which converts l2-bits code groups applied to the input into twoindependent densitymodulation pulse trains, namely one pulse train forsix bits of small weight and one integrator employing two time constantswhich are fed in the same time by the two said pulse trains and theoutput of which supplied the original analog signal.

UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Patent No- MauriceGeorges Bellanger et a1. Inventor(s) It is certified that error appearsin the above-identified patent and that said Letters Patent are herebycorrected as shown below:

Col. 4, line 6, "smaller" should be -smallest--;

Col. 6, line 30, should read:

E 0 2: n n -n Col. 8, line 44, "the" should be -two--,-

Col. 8, line 54, after "gate" should be l8--;

Signed and Scaled this sixth D y of January 1976 [SEAL] Arrest:

RUTH C. MASON C. MARSHALL DANN Arresting ()fjicer (mnmissimu-r ofParents and Trudemurkx UNITED STATES PATENT AND TRADEMARK OFFICECERTIFICATE OF CORRECTION PATENT NO. 1 3, 904,963

DATED INV ENTOR(S) I September 9, 1.975

MAURICE GEORGES BELLANGER and JACQUES LUCIEN DAGUET It is certified thaterror appears in the above-identified patent and that said LettersPatent are hereby corrected as shown betow:

ON THE TITLE PAGE Insert the fo1 lowing where appropriate:

"[30] FOREIGN APPLICATION PRIORITY DATA August 6, 1969 French.....6926970-7 Signed and Scaled this twenty-seventh D a 0f April 1 9 76[SEAL] A rresr:

RUTH C. MASON (mmnim'mu'r nj'lule'nls and Trademarks

1. A system for the transmission of analog signals by means of a pulsecode modulation, comprising a transmitter and a receiver, saidtransmitter comprising means to sample said analog signal at four timesthe maximum information frequency to be transmitted of said analogsignal, a coder coupled to said sampling means to convert linearly saidsampled signals to code groups comprising serial bits, a digital filtercoupled to said coder, said digital filter being formed as a low pass,half band filter of the nonrecursive type, and a digital compressorcoupled to said digital filter, said receiver comprising a digitalexpander having an output which is similar to the input to said digitalcompressor, a digital filtering device for interpolating between codegroups at the input means thereof to produce output code groups at atleast four times the frequency of the input code groups thereof, saiddigital filtering device comprising a plurality of nonrecursive filters,and a decoder being coupled to said digital filtering device forgenerating an output signal which is a reproduction of said analogsignal.
 2. A transmitter for the transmission of analog signals by meansof a pulse code modulation, comprising means to sample said analogsignal at least four times the maximum information frequency of saidanalog signal, a coder coupled to said sampling means to convertlinearly said sampled signals to code groups comprising serial bits, adigital filter coupled to said coder being formed as a low pass, halfband filter of the non-recursive type, and a digital compressor coupledto said digital filter.
 3. A transmitter as claimed in claim 2, whereinsaid coder comprises a four-slope coder in which said sampled signal isapplied to a duration modulator comprising two integrating networkshaving greatly differing time constants for pulse duration in accordancewith four difference slopes, the three slopes of which commences at afixed instant during each conversion period, means to derive 12-bit codegroups coupled to said integrating networks, said duration modulatorcomprising two digital counters coupled to said integrating networksrespectively, said digital counters being active one after the otherduring a half a conversion period and are thereafter converted into ashift register in order to supply the bits of a code group storedtherein in parallel as a serial bit output signal.
 4. A transmitter asclaimed in claim 3, wherein the zero point of said conversion is locatedin the center of its linear region, said region corresponding to 64times the bit of the smallest weight.
 5. A transmitter as claimed inclaim 2, wherein said digital filter comprises means to separate codegroups into code groups of even order and code groups of odd order, amultiplier in which the code groups of even order are multiplied by apredetermined weight co-efficient the magnitude of which is determinedfrom the central transfer co-efficient of said digital filter, aplurality of multipliers in which code groups of odd order aremultiplied by predetermined weight co-efficients whose magnitudes aredetermined from the odd transfer co-efficients of said digital filter,and a cascade cIrcuit of dynamic memories and combination devices forcombining the output signals of said multipliers in a predeterminedmanner.
 6. A receiver for a pulse code modulated signal comprising ananalog signal encoded as compressed digitally code groups, said receivercomprising a digital expander, a digital filter device for interpolatingbetween code groups at the input means thereof to produce output codegroups at least four times the frequency of the input code groupsthereof, said digital filtering device comprising non-recursive filtersand a decoder, said decoder being coupled to said digital device forgenerating an output signal which is a reproduction of said analogsignal.
 7. A receiver as claimed in claim 6, further comprising means toconvert the pulse code modulation signal from said digital filteringdevice into delta pulse code modulation by subtracting successive codegroups from each other, said conversion means being between said digitalfiltering device and said decoder.
 8. A receiver as claimed in claim 7,wherein said digital filtering device comprises a cascade circuit of twodevices each of said devices comprising a non-recursive digital filter,a delay circuit connected to the input means of said digital filter andan OR-gate connected to the output means of said digital filter, theoutput means of said delay circuit being connected to said OR-gatewhereby code groups present at the output means of said digital filterand code groups present at the output means of said delay circuitalternate with each other.
 9. A receiver as claimed in claim 8, whereinsaid non-recursive digital filter comprises a plurality of multipliersin which code groups at the filter input are multiplied by predeterminedweight co-efficients whose magnitudes are determined from the oddtransfer co-efficients of said digital filter, and a cascade circuit ofdynamic memories and combination device for combining the output signalof said multipliers in a predetermined manner.
 10. A receiver as claimedin claim 7, wherein said decoder comprises a device which converts12-bits code groups applied to the input into two independentdensity-modulation pulse trains, namely one pulse train for six bits ofsmall weight and one integrator employing two time constants which arefed in the same time by the two said pulse trains and the output ofwhich supplied the original analog signal.